The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Jan. 12, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Ling Chung, Hsinchu, TW;

Chun-Chih Cheng, Changhua, TW;

Ying-Liang Chuang, Hsinchu, TW;

Ming-Hsi Yeh, Hsinchu, TW;

Kuo-Bin Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/28 (2025.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H01L 21/28079 (2013.01); H01L 21/2855 (2013.01); H01L 21/76814 (2013.01); H01L 21/76834 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H10D 64/017 (2025.01); H10D 64/666 (2025.01); H10D 84/0137 (2025.01); H10D 84/038 (2025.01);
Abstract

Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.


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