The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Sep. 09, 2022
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Yuan-Huang Wei, Taichung, TW;

Chien-Hsien Wu, Taichung, TW;

Hsiu-Han Liao, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11531 (2017.01); H01L 27/11521 (2017.01); H10B 41/30 (2023.01); H10B 41/42 (2023.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10B 41/42 (2023.02); H10B 41/30 (2023.02); H10D 62/115 (2025.01);
Abstract

The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.


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