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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12519059 B1

PDFFull Text
Date of Patent:
Jan. 06, 2026

Filed:

Jan. 09, 2023

Semiconductor device and manufacturing method thereof

Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Tseng-Chieh Pan, New Taipei, TW;

Yu-Hsiang Wang, Miaoli County, TW;

Chi-Shin Wang, Hsinchu, TW;

Fan-Yi Hsu, Miaoli County, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;

Attorneys:

WPAT LAW

Anthony King

Primary Examiner:

Dale E Page

Assistant Examiner:

Quovaunda undefined Jefferson

Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53266 (2013.01); H01L 21/02068 (2013.01); H01L 21/02362 (2013.01); H01L 21/32135 (2013.01); H01L 21/324 (2013.01);
Abstract

The present disclosure provides a semiconductor structure, including a substrate, a gate structure over the substrate, including a work function layer over the substrate, a dielectric layer at least partially surrounding the gate structure, and a capping layer over the gate structure, wherein a bottom of the capping layer includes at least one protrusion protruding toward the substrate.

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Quick Actions:

Pan, Tseng-Chieh. (2026). Semiconductor device and manufacturing method thereof (U.S. Patent No. 12519059). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12519059

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