The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Mar. 08, 2023
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Chii Shang Hong, Bukit Katil, MY;

Li Fong Chong, Alor Gajah, MY;

Yee Beng Daryl Yeow, Batu Berendam, MY;

Edward Fürgut, Dasing, DE;

Mei Fen Hiew, Melaka, MY;

Azlina Kassim, Taman Bukit Cheng, MY;

Ralf Otremba, Kaufbeuren, DE;

Bernd Schmoelzer, Radenthein, AT;

Joon Shyan Tan, Seremban, MY;

Lee Shuang Wang, Bukit Baru, MY;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 23/315 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/49503 (2013.01); H01L 23/49558 (2013.01); H01L 23/49562 (2013.01); H01L 24/40 (2013.01); H01L 24/48 (2013.01); H01L 2224/40257 (2013.01); H01L 2224/48257 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1811 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/182 (2013.01);
Abstract

A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.


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