The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Aug. 10, 2022
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc Nanjing Company, Limited, Nanjing, CN;

Inventors:

Min Han Hsu, Hsinchu, TW;

Jung-Chih Tsao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H01L 21/28088 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 64/017 (2025.01); H10D 64/667 (2025.01);
Abstract

A method of fabricating a semiconductor device includes forming a dummy gate structure over a semiconductor fin. The dummy gate structure includes a dummy gate stack and gate spacers along sidewalls of the dummy gate stack. The method further includes forming an inter-layer dielectric (ILD) layer surrounding the dummy gate structure, removing the dummy gate stack to provide an opening exposing a channel region of the semiconductor fin, depositing a gate dielectric layer over bottom and sidewalls of the opening and over the ILD layer, forming a doped work function material layer over the gate dielectric layer using an in-situ doping process, and depositing a gate electrode layer over the doped work function material layer.


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