The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jan. 31, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jyun-Hong Huang, Hsinchu, TW;

Hsin-Che Chiang, Taipei, TW;

Wei-Chih Kao, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 84/0128 (2025.01); H10D 84/0147 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01);
Abstract

A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming an active region extending in a first horizontal direction, forming an isolation structure surrounding the active region, forming a gate dielectric layer over the active region and the isolation structure, forming a gate electrode layer nested within the gate dielectric layer, and removing the gate electrode layer and a first portion of the gate dielectric layer over the isolation structure to form a trench. A second portion of the gate dielectric layer over the active region is left to form first protection features. The method further includes depositing a dielectric layer in the trench.


Find Patent Forward Citations

Loading…