The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

May. 08, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Yuan Chen, Hsinchu, TW;

Cheng-Chi Chuang, New Taipei, TW;

Chih-Hao Wang, Baoshan Township, TW;

Huan-Chieh Su, Tianzhong Township, TW;

Kuo-Nan Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6729 (2025.01); H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H01L 23/535 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0135 (2025.01); H10D 84/0149 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.


Find Patent Forward Citations

Loading…