The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jul. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ru-Shang Hsiao, Jhubei, TW;

Po-Ying Chen, Tainan, TW;

Chen-Bin Lin, Tainan, TW;

Jie Jay Sun, Hsinchu, TW;

I-Shan Huang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10D 1/47 (2025.01); H10D 1/68 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5228 (2013.01); H01L 21/76832 (2013.01); H01L 23/5223 (2013.01); H01L 23/5283 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01); H10D 1/474 (2025.01); H10D 1/692 (2025.01); H01L 23/5226 (2013.01);
Abstract

The present disclosure discloses a structure and a method directed to a semiconductor structure having a resistor structure and a metal-insulator-metal (MIM) capacitor structure formed by a single mask process. The semiconductor structure includes an interconnect structure on a substrate, a first insulating layer on the interconnect structure, first and second conductive plates on the first insulating layer and separated by a second insulating layer, a dielectric layer on the first conductive plate, and a third conductive plate on the dielectric layer. Bottom surfaces of the first and second conductive plates are coplanar.


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