The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2025
Filed:
May. 27, 2022
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Hsien-Feng Liao, Taichung, TW;
Jian-Hsing Lee, Hsinchu, TW;
Chieh-Yao Chuang, Kaohsiung, TW;
Ting-Yu Chang, Zhubei, TW;
Yeh-Ning Jou, Hsinchu, TW;
Shao-Chang Huang, Hsinchu, TW;
Kan-Sen Chen, Zhubei, TW;
Nai-Lun Cheng, Zhubei, TW;
Ching-Yi Hsu, Hsinchu, TW;
Yu-Chen Wu, New Taipei, TW;
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, Hsinchu, TW;
Abstract
A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends in a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend in the first direction. The second and third well regions have a second conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shielding structure.