The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Aug. 17, 2023
Applicant:

Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;

Inventors:

Zhi Tian, Shanghai, CN;

Hua Shao, Shanghai, CN;

Haoyu Chen, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/65 (2025.01); H10D 30/0221 (2025.01); H10D 30/0281 (2025.01); H10D 30/603 (2025.01); H10D 62/116 (2025.01); H10D 62/157 (2025.01); H10D 64/513 (2025.01);
Abstract

The present application discloses an HV device, comprising: a gate dielectric layer formed in a first trench and a second dielectric layer formed in a second trench. A second side face of a drain shallow trench isolation is aligned with a first side face of the first trench. A second side face of the second trench is aligned with a first side face of the drain shallow trench isolation. A drain high voltage diffusion region is formed in a first high voltage well region, and the drain shallow trench isolation is located in the drain high voltage diffusion region. A drain region is formed in a surface region of the drain high voltage diffusion region outside the first side face of the second dielectric layer. The present application also discloses a method for manufacturing an HV device.


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