The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Dec. 22, 2021
Applicant:

Xintec Inc., Taoyuan, TW;

Inventors:

Po-Han Lee, Taipei, TW;

Wei-Ming Chien, Taoyuan, TW;

Assignee:

XINTEC INC., Taoyuan, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/498 (2006.01); H10D 62/85 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49844 (2013.01); H10D 62/8503 (2025.01); H10D 64/258 (2025.01);
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface opposite thereto. A gallium nitride (GaN)-based device layer is formed on the first surface of the semiconductor substrate and has source, drain, and gate contact regions. First, second, and third through-substrate vias (TSVs) pass through the semiconductor substrate and are respectively electrically connected to the source, drain, and gate contact regions. An insulating liner layer is formed on the second surface of the semiconductor substrate and extends into the semiconductor substrate to separate the second and third TSVs from the semiconductor substrate. A semiconductor package assembly including the semiconductor device structure is also provided.


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