The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Feb. 22, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chih-Nan Lo, Hsinchu, TW;

Ming-Chi Huang, Hsinchu County, TW;

Hsin-Hsien Lu, Hsinchu, TW;

Ming-Hsi Yeh, Hsinchu, TW;

Kuo-Bin Huang, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H01L 21/02 (2006.01); H01L 21/3115 (2006.01); H01L 21/768 (2006.01); H01L 21/32 (2006.01);
U.S. Cl.
CPC ...
H10D 84/0151 (2025.01); H01L 21/02164 (2013.01); H01L 21/02323 (2013.01); H01L 21/02343 (2013.01); H01L 21/3115 (2013.01); H01L 21/76826 (2013.01); H01L 21/76828 (2013.01); H10D 84/0142 (2025.01); H10D 84/0144 (2025.01); H01L 21/32 (2013.01);
Abstract

The present disclosure provides a method for fabricating a semiconductor structure, including forming a dielectric layer over a first region and a second region of a substrate, wherein the second region is adjacent to the first region, increasing a thickness of the dielectric layer in the first region, including forming an oxygen capturing layer over the dielectric layer in the first region, including forming the oxygen capturing layer over the first region and the second region, and removing the oxygen capturing layer over the second region with a mask layer, performing an oxidizing operation from a top surface of the oxygen capturing layer to increase oxygen concentration of the oxygen capturing layer, removing the oxygen capturing layer over the first region, and forming a gate structure over the dielectric layer.


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