The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jun. 08, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Chieh Wang, Kaohsiung, TW;

Yueh-Ching Pai, Taichung, TW;

Huai-Tei Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 21/762 (2006.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 62/13 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H01L 21/027 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H10D 84/853 (2025.01); H01L 21/0206 (2013.01); H01L 21/02211 (2013.01); H01L 21/02271 (2013.01); H01L 21/02532 (2013.01); H01L 21/30625 (2013.01); H01L 21/3065 (2013.01); H01L 21/76224 (2013.01); H10D 30/751 (2025.01); H10D 62/021 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 84/0167 (2025.01); H10D 84/0172 (2025.01); H10D 84/0188 (2025.01); H10D 84/0191 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/859 (2025.01); H01L 21/0273 (2013.01); H01L 21/26513 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01);
Abstract

A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.


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