The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

May. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chieh-Ping Wang, Taichung, TW;

Ting-Gang Chen, Taipei, TW;

Tai-Chun Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/017 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 62/115 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01);
Abstract

Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming fins from a substrate, forming a dummy gate stack over portions of the fins, forming epitaxial source/drain regions adjacent the dummy gate stack, depositing a first inter-layer dielectric (ILD) over the epitaxial source/drain region, replacing the dummy gate stack with a first gate stack, forming a trench through the first gate stack and into an isolation region under the first gate stack, and forming a dielectric layer in the trench by an atomic layer deposition process, wherein the dielectric layer is non-conformal.


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