The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2025
Filed:
Oct. 30, 2023
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Tse-An Chen, Taoyuan, TW;
Lain-Jong Li, Hsinchu, TW;
Wen-Hao Chang, Hsinchu, TW;
Chien-Chih Tseng, New Taipei, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 48/36 (2025.01); H01L 21/02 (2006.01); H01L 21/78 (2006.01); H10D 62/80 (2025.01); H10D 86/01 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10D 48/362 (2025.01); H01L 21/02458 (2013.01); H01L 21/02488 (2013.01); H01L 21/7806 (2013.01); H10D 62/80 (2025.01); H10D 86/0214 (2025.01); H10D 99/00 (2025.01);
Abstract
A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.