The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2025

Filed:

Jan. 09, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shen-Yang Lee, Miaoli County, TW;

Hsiang-Pi Chang, New Taipei, TW;

Huang-Lin Chao, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A method for tuning a threshold voltage of a transistor is disclosed. A channel layer is formed over a substrate. An interfacial layer is formed over and surrounds the channel layer. A gate dielectric layer is formed over and surrounds the interfacial layer. A dipole layer is formed over and wraps around the gate dielectric layer by performing a cyclic deposition etch process, and the dipole layer includes dipole metal elements and has a substantially uniform thickness. A thermal drive-in process is performed to drive the dipole metal elements in the dipole layer into the gate dielectric layer to form an interfacial dipole surface, and then the dipole layer is removed.


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