The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2025
Filed:
Jun. 23, 2022
Applicant:
Yangtze Memory Technologies Co., Ltd., Hubei, CN;
Inventors:
Peng Chen, Hubei, CN;
Houde Zhou, Hubei, CN;
Assignee:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 24/05 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/0233 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92247 (2013.01);
Abstract
The present disclosure provides a semiconductor structure, comprising a die/die stack attached on a substrate, a conductive top block covering a top surface of the die/die stack, and a plurality of ground wires conductively connect the conductive top block and to the substrate. The conductive top block, the plurality of ground wires, and the substrate form a Faraday cage to provide an electromagnetic interference shielding of the die/die stack.