The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Sep. 02, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ian Alexander Young, Olympia, WA (US);

Dmitri Evgenievich Nikonov, Beaverton, OR (US);

Chia-Ching Lin, Portland, OR (US);

Tanay A. Gosavi, Portland, OR (US);

Ashish Verma Penumatcha, Beaverton, OR (US);

Kaan Oguz, Portland, OR (US);

Punyashloka Debashis, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 52/80 (2023.01); G06N 3/063 (2023.01); G11C 11/16 (2006.01); G11C 11/18 (2006.01); H01F 10/32 (2006.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01); H10N 52/00 (2023.01);
U.S. Cl.
CPC ...
H10N 52/80 (2023.02); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/18 (2013.01); H01F 10/3254 (2013.01); H01F 10/3272 (2013.01); H01F 10/329 (2013.01); H10B 61/22 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02); H10N 52/00 (2023.02); G06N 3/063 (2013.01);
Abstract

A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.


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