The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Mar. 29, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Tsung-Sheng Kang, Ballston Lake, NY (US);

Alexander Reznicek, Troy, NY (US);

Sagarika Mukesh, Albany, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/43 (2025.01); H01L 23/528 (2006.01); H10D 30/00 (2025.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 23/5286 (2013.01); H10D 30/019 (2025.01); H10D 30/43 (2025.01); H10D 30/501 (2025.01); H10D 30/658 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01);
Abstract

Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first pair of field effect transistors (FETs). Additionally, the semiconductor structure includes a second pair of FETs. Further, the semiconductor structure includes a shallow gate cut that separates a first pair of gates, a first pair of channels, and a first pair of source/drain (S/D) epitaxies of the first pair of FETs. Additionally, the first pair of S/D epitaxies are wired to a backside power rail (BPR) by a backside contact. Further, the semiconductor structure includes a deep gate cut that separates a second pair of S/D epitaxies of the second pair of FETs. Additionally, one of the second pair of S/D epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact. Further, another of the second pair of S/D epitaxies is wired to the BPR by a backside contact.


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