The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Feb. 10, 2021
Applicant:

Wolfspeed, Inc., Durham, NC (US);

Inventors:

Saptharishi Sriram, Cary, NC (US);

Jia Guo, Apex, NC (US);

Assignee:

Wolfspeed, Inc., Durham, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/17 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/475 (2025.01); H10D 30/015 (2025.01); H10D 30/4732 (2025.01); H10D 30/4755 (2025.01); H10D 62/357 (2025.01); H10D 62/8503 (2025.01); H10D 64/111 (2025.01); H10D 64/251 (2025.01); H10D 64/411 (2025.01); H10D 62/343 (2025.01); H10D 64/256 (2025.01);
Abstract

An apparatus to address gate lag effect and/or other negative performance includes a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer may include a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at least in the substrate. In particular, the p-region extends toward a source side of the substrate; and the p-region extends toward a drain side of the substrate.


Find Patent Forward Citations

Sriram, Saptharishi. (2025). Group iii-nitride high-electron mobility transistors with gate connected buried p-type layers and process for making the same (U.S. Patent No. 12484244). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12484244

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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