The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Feb. 18, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Bo-Feng Young, Taipei, TW;

Sheng-Chen Wang, Hsinchu, TW;

Sai-Hooi Yeong, Hsinchu County, TW;

Yu-Ming Lin, Hsinchu, TW;

Chao-I Wu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 53/40 (2023.01); H10B 51/20 (2023.01); H10B 51/40 (2023.01); H10B 53/20 (2023.01); H10B 61/00 (2023.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); H10B 51/40 (2023.02); H10B 53/20 (2023.02); H10B 53/40 (2023.02); H10B 61/22 (2023.02); H10N 50/85 (2023.02);
Abstract

A semiconductor chip including a semiconductor substrate, an interconnect structure and memory devices is provided. The semiconductor substrate includes first transistors, and the first transistors are negative capacitance field effect transistors. The interconnect structure is disposed over the semiconductor substrate and electrically connected to the first transistors, and the interconnect structure includes stacked interlayer dielectric layers, interconnect wirings, and second transistors embedded in the stacked interlayer dielectric layers. The memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors.


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