The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jan. 04, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yee-Chia Yeo, Hsinchu, TW;

Sung-Li Wang, Zhubei, TW;

Chi On Chui, Hsinchu, TW;

Jyh-Cherng Sheu, Hsinchu, TW;

Hung-Li Chiang, Taipei, TW;

I-Sheng Chen, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/62 (2025.01); H01L 23/522 (2006.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01); H10D 62/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/62 (2025.01); H01L 23/5226 (2013.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 62/151 (2025.01); H10D 84/0133 (2025.01); H10D 84/017 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 84/85 (2025.01); H10D 84/853 (2025.01); H10D 62/83 (2025.01); H10D 84/0167 (2025.01);
Abstract

A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.


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