The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Apr. 28, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shih-Hao Tseng, Hsinchu, TW;

Hung-Jui Kuo, Hsinchu, TW;

Ming-Che Ho, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/36 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/31 (2013.01); H01L 21/56 (2013.01); H01L 23/36 (2013.01); H01L 25/0657 (2013.01);
Abstract

A semiconductor package includes a first integrated circuit, a first passivation layer, a second passivation layer, a thermal pattern, an adhesive layer and a second integrated circuit. The first integrated circuit is encapsulated by an encapsulant. The first passivation layer is disposed over the first integrated circuit and the encapsulant. The second passivation layer is disposed over the first passivation layer. The thermal pattern is disposed in the first passivation layer and the second passivation layer. The adhesive layer is disposed over the second passivation layer and in direct contact with the thermal pattern. The second integrated circuit is adhered to the first integrated circuit through the adhesive layer.


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