The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Dec. 22, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 23/522 (2006.01); H10D 30/67 (2025.01); H01L 23/532 (2006.01); H10D 64/62 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 23/5226 (2013.01); H10D 30/6729 (2025.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H01L 23/53209 (2013.01); H01L 23/53257 (2013.01); H10D 30/6735 (2025.01); H10D 64/62 (2025.01);
Abstract
Methods of forming self-aligned vias and devices having self-aligned vias are provided. In some embodiments, a method includes forming a first via on a conductive layer. A mask is formed over the conductive layer, and the mask has an opening overlying a portion of the conductive layer and at least partially overlying the first via. A first line end of the conductive layer is formed by selectively removing the portion of the conductive layer, with the first via being aligned with the first line end of the conductive layer.