The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jan. 05, 2024
Applicant:

Micron Technology, Inc., Bosie, ID (US);

Inventors:

Tomoharu Tanaka, Yokohama, JP;

Yoshihiko Kamata, Yokohama, JP;

Yoshiaki Fukuzumi, Yokohama, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 5/06 (2006.01); G11C 5/14 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 5/145 (2013.01); G11C 5/063 (2013.01); G11C 16/30 (2013.01);
Abstract

A memory device includes an array of strings of memory cells, a local bitline coupled with a plurality of the strings of memory cells, and a sense transistor having a gate terminal coupled with the local bitline. The memory device further includes a series of transistors have a data read path between a source line and the sense transistor and between the sense transistor and a global bitline that is coupled with a page buffer. A micropump is integrated within the series of transistors. Control logic is coupled with the series of transistors and to, during a read operation of a memory cell of the array and in response to the sense transistor turning on, activate the micropump to cause a constant read current to flow between the global bitline and the source line.


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