The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2025
Filed:
May. 24, 2022
Applicants:
Invention and Collaboration Laboratory Pte. Ltd., Singapore, SG;
Etron Technology, Inc., Hsinchu, TW;
Inventors:
Chao-Chun Lu, Hsinchu, TW;
Li-Ping Huang, Hsinchu, TW;
Assignees:
INVENTION AND COLLABORATION LABORATORY PTE. LTD., Singapore, SG;
ETRON TECHNOLOGY, INC., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10B 12/00 (2023.01); H10D 30/63 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 62/102 (2025.01); H10B 12/053 (2023.02); H10B 12/488 (2023.02); H10D 30/6715 (2025.01); H10D 30/6757 (2025.01); H10D 64/01 (2025.01); H10D 64/512 (2025.01); H10D 30/637 (2025.01); H10D 64/513 (2025.01);
Abstract
A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer and a first conductive region. At least a portion of the gate conductive region is disposed below a surface of the substrate. The gate dielectric layer surrounds a bottom wall and sidewalls of the gate conductive region. A bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.