The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Feb. 22, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Wei Chen, Hsinchu, TW;

Jo-Chun Hung, Hsinchu, TW;

Chih-Wei Lee, New Taipei, TW;

Hui-Chi Chen, Zhudong Township, Hsinchu County, TW;

Hsin-Han Tsai, Hsinchu, TW;

Hsiang-Ju Liao, Changhua County, TW;

Yi-Lun Li, Taipei, TW;

Cheng-Lung Hung, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 86/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H01L 21/02614 (2013.01); H01L 21/76855 (2013.01); H01L 21/76886 (2013.01); H01L 21/76888 (2013.01); H10D 30/62 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 62/119 (2025.01); H10D 62/123 (2025.01); H10D 64/01 (2025.01); H10D 64/667 (2025.01); H10D 84/0158 (2025.01); H10D 86/011 (2025.01);
Abstract

A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes removing the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor lavers. The method further includes forming a gate dielectric layer to wrap around the semiconductor nanostructures and forming a first metal-containing layer over the gate dielectric layer to wrap around the semiconductor nanostructures. In addition, the method includes introducing oxygen-containing plasma on the first metal-containing layer to transform an upper portion of the first metal-containing layer into a metal oxide layer. The method includes forming a second metal-containing layer over the metal oxide layer.


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