The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

May. 27, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Sheng-Tsung Wang, Hsinchu, TW;

Chia-Hao Chang, Hsinchu, TW;

Lin-Yu Huang, Hsinchu, TW;

Cheng-Chi Chuang, New Taipei, TW;

Chih-Hao Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10D 30/62 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01); H10D 30/6219 (2025.01); H10D 64/514 (2025.01);
Abstract

Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.


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