The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Jan. 21, 2022
Applicant:

China Electronics Technology Group Corporation No.24 Research Institute, Chongqing, CN;

Inventors:

Kaizhou Tan, Chongqing, CN;

Tian Xiao, Chongqing, CN;

Jiahao Zhang, Chongqing, CN;

Yonghui Yang, Chongqing, CN;

Hequan Jiang, Chongqing, CN;

Ruzhang Li, Chongqing, CN;

Peijian Zhang, Chongqing, CN;

Yi Zhong, Chongqing, CN;

Peng Wang, Chongqing, CN;

Yuxin Wang, Chongqing, CN;

Xiaojun Fu, Chongqing, CN;

Zhaohuan Tang, Chongqing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/00 (2025.01); H10D 62/10 (2025.01); H10D 8/00 (2025.01); H10D 10/40 (2025.01); H10D 12/00 (2025.01); H10D 30/66 (2025.01);
U.S. Cl.
CPC ...
H10D 64/115 (2025.01); H10D 62/109 (2025.01); H10D 64/112 (2025.01); H10D 8/00 (2025.01); H10D 10/40 (2025.01); H10D 12/441 (2025.01); H10D 30/66 (2025.01);
Abstract

The disclosure provides a power semiconductor device and manufacturing method thereof. A plurality of second resistive field plate structures extending through an epitaxial layer in a first direction into a substrate are arranged in a termination region of the epitaxial layer and the plurality of second resistive field plate structures are arranged radially in a first plane. A plurality of tightly coupled second resistive field plates extending from a side close to a cell region to a side far away from the cell region form a more uniform three-dimensional electric field distribution diverging around the cell region, which optimizes a guiding and binding effect on a charge in a space depletion region of the cell region and improves a withstand voltage performance of the whole power semiconductor device.


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