The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Jan. 11, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tzu-Yu Chen, Kaohsiung, TW;

Sheng-Hung Shih, Hsinchu, TW;

Fu-Chen Chang, New Taipei, TW;

Kuo-Chi Tu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 53/30 (2023.01); H01L 23/48 (2006.01); H10D 64/68 (2025.01); H10D 84/80 (2025.01);
U.S. Cl.
CPC ...
H10B 53/30 (2023.02); H01L 23/481 (2013.01); H10D 64/689 (2025.01); H10D 84/80 (2025.01);
Abstract

Various embodiments of the present disclosure are directed towards a memory cell in which an interfacial layer is on a bottom of a ferroelectric layer, between a bottom electrode and a ferroelectric layer. The interfacial layer is a different material than the bottom electrode and the ferroelectric layer and has a top surface with high texture uniformity compared to a top surface of the bottom electrode. The interfacial layer may, for example, be a dielectric, metal oxide, or metal that is: (1) amorphous; (2) monocrystalline; (3) crystalline with low grain size variation; (4) crystalline with a high percentage of grains sharing a common orientation; (5) crystalline with a high percentage of grains having a small grain size; or 6) any combination of the foregoing. It has been appreciated that such materials lead to high texture uniformity at the top surface of the interfacial layer.


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