The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Apr. 03, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eunkyul Oh, Suwon-si, KR;

Chonghee Lee, Suwon-si, KR;

Keunho Jang, Suwon-si, KR;

Yunrae Cho, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/05 (2013.01); H01L 24/48 (2013.01); H01L 24/81 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81411 (2013.01); H01L 2224/81439 (2013.01); H01L 2224/81444 (2013.01); H01L 2224/81455 (2013.01); H10B 80/00 (2023.02);
Abstract

A semiconductor package includes a package substrate including a redistribution layer including first pads and second pads on an upper surface thereof and a solder mask layer having an opening exposing the first pads entirely and exposing at least portion of each of the second pads, a semiconductor chip on the upper surface of the package substrate and including connection pads electrically connected to the redistribution layer, connection bumps below the semiconductor chip and connecting the connection pads to the first pads, and a non-conductive film layer between the semiconductor chip and the package substrate, wherein the second pads are respectively disposed on both sides of the first pads at least in a first direction, and the connection bumps are spaced apart from the second pads and the solder mask layer in the first direction.


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