The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

May. 20, 2022
Applicants:

Changxin Memory Technologies, Inc., Hefei, CN;

Beijing Superstring Academy of Memory Technology, Beijing, CN;

Inventors:

Guangsu Shao, Hefei, CN;

Pan Yuan, Hefei, CN;

Minmin Wu, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/304 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/3043 (2013.01);
Abstract

The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate, the substrate including a first semiconductor material layer, a silicon-germanium compound layer and a second semiconductor material layer that are stacked sequentially; forming, in the substrate, first trenches extending along a first direction and second trenches extending along a second direction, and the first trenches and the second trenches separating the substrate into a plurality of spaced pillar structures; doping the pillar structures, such that the silicon-germanium compound layer forms a channel region; and forming a dielectric layer on an outer peripheral surface of each of the pillar structures, and a gate on an outer peripheral surface of the dielectric layer, the gate being opposite to at least a part of the channel region.


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