The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jun. 01, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsin-Yi Lee, Hsinchu, TW;

Yen-Tien Tung, Hsinchu, TW;

Ji-Cheng Chen, Hsinchu, TW;

Weng Chang, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/28 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/28088 (2013.01); H10D 30/031 (2025.01); H10D 30/6739 (2025.01); H10D 64/017 (2025.01); H10D 84/83 (2025.01); H10D 30/6757 (2025.01);
Abstract

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, with the semiconductor region being exposed to the trench, forming a gate dielectric layer extending into the trench, and depositing a work-function tuning layer on the gate dielectric layer. The work-function tuning layer comprises aluminum and carbon. The method further includes depositing a p-type work-function layer over the work-function tuning layer, and performing a planarization process to remove excess portions of the p-type work-function layer, the work-function tuning layer, and the gate dielectric layer to form a gate stack.


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