The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Feb. 21, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wen-Sheh Huang, Hsinchu, TW;

Yu-Hsiang Chen, Hsinchu, TW;

Chii-Ping Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 1/20 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/3171 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H10D 1/20 (2025.01); H10D 30/024 (2025.01); H10D 30/43 (2025.01); H10D 30/6211 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01); H01L 2224/0401 (2013.01);
Abstract

A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.


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