The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Jun. 08, 2023
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Ruo Fang Zhang, Wuhan, CN;

Enbo Wang, Wuhan, CN;

Haohao Yang, Wuhan, CN;

Qianbing Xu, Wuhan, CN;

Yushi Hu, Wuhan, CN;

Fushan Zhang, Wuhan, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); G11C 5/06 (2006.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 5/063 (2013.01); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

In a three-dimensional memory device, an interconnect structure is formed over a substrate and a first deck is formed over the interconnect structure. The first deck includes alternating first insulating layers and first word line layers, and a first channel structure extending through the first stack. The first channel structure has a first channel dielectric region and a first channel layer. The first channel dielectric region is formed along sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers. The first channel layer is formed along the first channel dielectric region, and includes a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack at an interface of the interconnect structure, the first channel structure and the first stack.


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