The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
Jun. 25, 2021
Intel Corporation, Santa Clara, CA (US);
Juan G. Alzate-Vinasco, Tigard, OR (US);
Travis W. Lajoie, Forest Grove, OR (US);
Elliot N. Tan, Portland, OR (US);
Kimberly Pierce, Beaverton, OR (US);
Shem Ogadhoh, West Linn, OR (US);
Abhishek A. Sharma, Portland, OR (US);
Bernhard Sell, Portland, OR (US);
Pei-Hua Wang, Hillsboro, OR (US);
Chieh-Jen Ku, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.