The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2025
Filed:
Aug. 08, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Yun Lee, Taipei County, TW;
Chen-Ming Lee, Taoyuan County, TW;
Fu-Kai Yang, Hsinchu, TW;
Yi-Jyun Huang, New Taipei, TW;
Sheng-Hsiung Wang, Hsinchu County, TW;
Mei-Yun Wang, Hsin-Chu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu, TW;
Abstract
An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate above the isolation feature, and a gate structure disposed directly over the isolation feature. The integrated circuit further includes a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, and a first etch stop layer disposed between the first dielectric layer and the isolation feature. The integrated circuit further includes a second dielectric layer disposed directly above the first dielectric layer, and a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer. The first etch stop layer is also disposed between the gate structure and the second etch stop layer. A conductive feature is directly above the isolation feature and directly contacting the first dielectric layer.