The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Dec. 23, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Anil Sharma, Portland, OR (US);

Wilfred Gomes, Portland, OR (US);

Christopher M. Pelto, Beaverton, OR (US);

Mark C. Phillips, Portland, OR (US);

Swaminathan Sivakumar, Beaveton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); G11C 5/14 (2006.01); G11C 11/412 (2006.01); H01L 23/42 (2006.01);
U.S. Cl.
CPC ...
H10B 10/18 (2023.02); G11C 11/412 (2013.01); H01L 23/42 (2013.01); G11C 5/141 (2013.01);
Abstract

Stitched dies having a cooling structure are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies. A plurality of microfluidic channels is coupled to the first side of the first and second dies.


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