The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2025
Filed:
May. 24, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Yung-Hsiang Chan, Taichung, TW;
An-Hung Tai, Hsinchu, TW;
Hui-Chi Chen, Zhudong Township, TW;
Jui Fu Chueh, Taipei, TW;
Yen-Ta Lin, Taipei, TW;
Ming-Chi Huang, Zhubei, TW;
Cheng-Chieh Tu, Hsinchu, TW;
Jian-Hao Chen, Hsinchu, TW;
Kuo-Feng Yu, Zhudong Township, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.