The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jul. 25, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Ping-Wei Wang, Hsinchu, TW;

Lien-Jung Hung, Hsinchu, TW;

Kuo-Hsiu Hsu, Hsinchu, TW;

Kian-Long Lim, Hsinchu, TW;

Yu-Kuan Lin, Hsinchu, TW;

Chia-Hao Pao, Hsinchu, TW;

Chih-Chuan Yang, Hsinchu, TW;

Shih-Hao Lin, Hsinchu, TW;

Choh Fei Yeap, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); H01L 21/66 (2006.01); H01L 23/528 (2006.01); H04N 21/426 (2011.01); H10B 41/35 (2023.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); G11C 11/412 (2013.01); G11C 11/419 (2013.01); H01L 22/12 (2013.01); H01L 23/528 (2013.01); H04N 21/42692 (2013.01); H10B 10/00 (2023.02); H10B 41/35 (2023.02); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01); H01L 2924/1437 (2013.01);
Abstract

A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.


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