The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Aug. 12, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Sheng Lin, Zhubei, TW;

Chin-Fu Kao, Taipei, TW;

Tsung-Yang Hsieh, Taipei, TW;

Jyun-Lin Wu, Hsinchu, TW;

Yao-Chun Chuang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/15 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/538 (2013.01); H01L 21/02433 (2013.01); H01L 23/145 (2013.01); H01L 23/147 (2013.01); H01L 23/15 (2013.01); H01L 23/562 (2013.01); H01L 25/0655 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/05432 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/15787 (2013.01); H01L 2924/15788 (2013.01);
Abstract

A first integrated circuit (IC) die includes a first substrate. A second IC die includes a second substrate. At least one of the first substrate or the second substrate has a first surface orientation. The first IC die is spaced apart from the second IC die. A third die electrically interconnects the first IC die to the second IC die. The third die includes a third substrate having a second surface orientation. The second surface orientation is different from the first surface orientation.


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