The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2025
Filed:
Mar. 30, 2022
Intel Corporation, Santa Clara, CA (US);
Leonard P. Guler, Hillsboro, OR (US);
Mauro J. Kobrinsky, Portland, OR (US);
Mohit K. Haran, Hillsboro, OR (US);
Marni Nabors, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Charles H. Wallace, Portland, OR (US);
Allen B. Gardiner, Portland, OR (US);
Sukru Yemenicioglu, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.