The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Aug. 04, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tzuan-Horng Liu, Taoyuan, TW;

Hao-Yi Tsai, Hsinchu, TW;

Kris Lipu Chuang, Hsinchu, TW;

Hsin-Yu Pan, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 24/16 (2013.01); H01L 24/20 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/214 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/73267 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01);
Abstract

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a first die disposed on and electrically coupled to a first redistribution structure and laterally covered by a first insulating encapsulation, a second die disposed over the first die and laterally covered by a second insulating encapsulation, a second redistribution structure interposed between and electrically coupled to the first and second dies, a third redistribution structure disposed on the second die and opposite to the second redistribution structure, and at least one thermal-dissipating feature embedded in a dielectric layer of the third redistribution structure and electrically isolated from a patterned conductive layer of the third redistribution structure through the dielectric layer. Through substrate vias of the first die are physically connected to the second redistribution structure or the first redistribution structure. The thermal-dissipating feature is thermally coupled to a back surface of the second die.


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