The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Aug. 08, 2022
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Kai-Ming Yang, Hsinchu County, TW;

Chen-Hao Lin, Keelung, TW;

Cheng-Ta Ko, Taipei, TW;

John Hon-Shing Lau, New Territories, HK;

Yu-Hua Chen, Hsinchu, TW;

Tzyy-Jang Tseng, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/40 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/15 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H05K 1/11 (2006.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01); H05K 3/32 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4038 (2013.01); H01L 21/4846 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/76898 (2013.01); H01L 23/145 (2013.01); H01L 23/147 (2013.01); H01L 23/15 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H05K 1/11 (2013.01); H05K 1/112 (2013.01); H05K 1/142 (2013.01); H05K 1/183 (2013.01); H05K 3/32 (2013.01); H05K 3/4682 (2013.01); H01L 23/49816 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/8385 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15311 (2013.01); H05K 1/185 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/1469 (2013.01); Y10T 29/4913 (2015.01); Y10T 29/49146 (2015.01); Y10T 29/49165 (2015.01);
Abstract

A method of manufacturing package structure includes following steps. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.


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