The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2025
Filed:
Apr. 08, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Meng-Pei Lu, Hsinchu, TW;
Shin-Yi Yang, Hsinchu, TW;
Cian-Yu Chen, Hsinchu, TW;
Yun-Chi Chiang, Hsinchu, TW;
Ming-Han Lee, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53271 (2013.01); H01L 21/76807 (2013.01); H01L 21/7682 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53209 (2013.01); H01L 23/53295 (2013.01); H01L 21/76831 (2013.01); H01L 21/76846 (2013.01);
Abstract
A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes an interconnect structure which includes a topological material. The topological material includes a topological insulator, a topological semimetal, or a combination thereof. A method for manufacturing the semiconductor device is also disclosed.