The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Mar. 10, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Changhan Kim, Boise, ID (US);

Chet E. Carter, Boise, ID (US);

Cole Smith, Boise, ID (US);

Collin Howder, Meridian, ID (US);

Richard J. Hill, Boise, ID (US);

Jie Li, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/41 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/0214 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/0223 (2013.01); H01L 21/02636 (2013.01); H01L 21/31111 (2013.01); H01L 23/528 (2013.01); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 41/41 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10D 30/0411 (2025.01); H10D 30/0413 (2025.01); H10D 30/683 (2025.01); H10D 30/689 (2025.01); H10D 30/693 (2025.01); H10D 62/292 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01); H10D 64/679 (2025.01); H10D 64/685 (2025.01); H10D 64/693 (2025.01); H01L 21/02255 (2013.01);
Abstract

Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.


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