The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Nov. 22, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kai-Hsuan Lee, Hsinchu, TW;

Chia-Ta Yu, New Taipei, TW;

Cheng-Yu Yang, Xihu Township, TW;

Sheng-Chen Wang, Hsinchu, TW;

Sai-Hooi Yeong, Zhubei, TW;

Feng-Cheng Yang, Zhudong Township, TW;

Yen-Ming Chen, Chu-Pei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/13 (2025.01); H01L 21/027 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H10B 10/00 (2023.01); H10D 62/00 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 21/0273 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H10B 10/18 (2023.02); H10D 62/021 (2025.01); H10D 62/151 (2025.01); H10D 64/021 (2025.01); H10D 84/013 (2025.01); H10D 84/0135 (2025.01); H10D 84/0158 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 62/822 (2025.01); H10D 84/017 (2025.01);
Abstract

A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.


Find Patent Forward Citations

Loading…