The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Nov. 19, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Adel A. Elsherbini, Tempe, AZ (US);

William J. Lambert, Chandler, AZ (US);

Krishna Bharath, Phoenix, AZ (US);

Shawna M. Liff, Scottsdale, AZ (US);

Nicolas Butzen, Portland, OR (US);

Georgios Dogiamis, Chandler, AZ (US);

Gerald S. Pasdast, San Jose, CA (US);

Vivek Kumar Rajan, Portland, OR (US);

Sathya Narasimman Tiagaraj, San Jose, CA (US);

Timothy Francis Schmidt, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 23/481 (2013.01); H01L 23/5223 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01);
Abstract

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.


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