The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2025
Filed:
Aug. 04, 2022
Micron Technology, Inc., Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A lining is formed in and that less-than-fills the cavity atop treads of the stairs. Individual of the treads comprise conducting material of one of the first tiers in the finished-circuitry construction. The lining that is atop the treads is replaced with at least one of metal material, polysilicon, or SiGe and insulative material is provided in remaining volume of the cavity directly above the at least one of the metal material, the polysilicon, or the SiGe. Conductive vias are formed through the insulative material and the at least one of the metal material, the polysilicon, or the SiGe. Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Other embodiments, including structure, are disclosed.