The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2025
Filed:
Oct. 24, 2023
Samsung Electronics Co., Ltd., Suwon-si, KR;
Jangwoon Sung, Suwon-si, KR;
Lei Tian, Boston, MA (US);
Hao Wang, Boston, MA (US);
Jiabei Zhu, Boston, MA (US);
Myungjun Lee, Suwon-si, KR;
Wookrae Kim, Suwon-si, KR;
Seungbeom Park, Suwon-si, KR;
Junho Shin, Suwon-si, KR;
Hojun Lee, Suwon-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do, KR;
TRUSTEES OF BOSTON UNIVERSITY, Boston, MA (US);
Abstract
A substrate inspection apparatus includes a light irradiator including an objective lens and a plurality of optical fibers. The objective lens is configured to irradiate light to an illumination area on a semiconductor substrate having a plurality of circuit pattern layers, the plurality of optical fibers are adjacent a periphery of the objective lens and are configured to irradiate the light to a peripheral area adjacent the illumination area. A light generator is configured to generate the light. The light generator is configured to change an irradiation angle of the light to selectively irradiate the light to one or more of the objective lens and the plurality of optical fibers. A light analyzer is configured to obtain images of the circuit pattern layers from the light reflected from the illumination area and the peripheral area. The light analyzer is configured to model each of the circuit pattern layers of the semiconductor substrate to obtain image models and to measure an overlay between the circuit pattern layers through the images and the image models.